osmosis Silicon Valley 2025

Agenda

9:30 am - 10:00 am

Registration and check-in 

Coffee and networking with your peers.

10:00 am - 10:05 am

Welcome/Intro

Nidhi Jain | AE Manager, Functional Verification 

10:05 am - 10:45 am

Revolutionizing Chip Development with AI and Next-Gen Verification Solutions

Abhi Kolpekwar | VP & GM, Digital Verification Technologies Division | Siemens EDA

Advances in AI/ML are driving a new era of chip design and verification, and in this keynote our VP&GM Abhi Kolpekwar will share Siemens EDA's long-term vision and investments in this area, including the critical role formal verification will play going forward.

10:45 am - 11:20 am

Automated Trust and Assurance for ASIC and FPGA Designs: Mitigating Security Risks with Formal Verification

Mitchell Poplingher | ASIC & FPGA Engineer Senior Staff | Lockheed Martin

We have all heard in the news about various data hacks and security breaches. These attacks often take advantage of some sort of unknown weakness in the design. To reduce these risks, trust and security verification is starting to become a requirement for ASIC and FPGA designs along with traditional functional verification. Recently, best practices to mitigate an exploitative attack have been documented. Examples include the Microelectronics Assurance Framework (MAF) Guidelines and the common weakness enumeration (CWEs) database. These documents have become a foundation for trust assurance requirements for microelectronic development on government programs. Manual review and inspection by experts are valuable but not sufficient. Formal verification technology can be applied to the automate the process to identify vulnerabilities and weaknesses in a design under test. Automated trust assurance tools, like the Siemens EDA Verify Trust tool, are now available to support these requirements.

In this presentation, we will introduce Questa Verify Trust and discuss some experiences and initial results from two projects at Lockheed Martin. An objective is to verify the incoming IPs for Trust, as incoming 3rd party RTL IPs may introduce security-relevant weaknesses and vulnerabilities. Another project must complete Trust Verification as a critical step of the Defense Microelectronics Activity (DMEA) trusted flow.

11:20 am - 11:55 am

Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems

Benjamin Ting | Principal Engineer | Microsoft

This presentation describes the development and implementation of a formal-based application flow to successfully address the unique challenges encountered in dynamically retargeting connectivity verification to multiple variants of large-scale, complex FPGA-based, AI-centric cloud hardware designs.

The key objective of this methodology was to establish a framework for both experts and non-experts alike that ensures simplicity, reusability, and scalability, from block to-system level, static and dynamic connectivity verification; while also supporting the comprehensive exposition of the design hierarchies required by backend physical tools, in conjunction with the automated generation of grouped assertions and parallel execution on the compute grid.

With this flow we successfully uncovered RTL bugs in minutes - a task that weeks of simulation-based regressions had failed to accomplish (and invalidate our initial assumption that the designs were correct by construction). We will share a sampling of results. 

12:00 noon - 1:00 pm

Lunch and Networking

1:00 pm - 1:35 pm

Tackling formal verification of larger designs using a modular approach

Ratish Punnoose | Distinguished Member of Technical Staff | Sandia National Labs

Performing formal verification of an SoC type design in one go is limited by the tractability of the formal checks as well as by the complexity of writing an assertion that captures the full behavior.

We describe approaches to perform verification in a modular way while maintaining assume-guarantee reasoning between the verification units.

1:35 pm - 2:10 pm

SLEC Flow: Leveraging Formal in Math Primitive Verification Closure

Abhiram Dronavalli | Design Verification Engineer | Microsoft
Sudha Raman | Senior Verification Engineer | Microsoft

This presentation will describe setup, challenges and learnings with INT36 functions verification.

2:10 pm - 3:00 pm

The Formal Promise Realized:  Why now is the time for formal in the mainstream 

Chris Giles | Director of Product Management, Static and Formal | Siemens EDA

For year, Formal verification has promised to change how teams verify designs.  While adoption of Formal is generally increasing, only a handful of teams in the industry leverage the full power of formal in the mainstream.  This session will discuss recent technical and methodology breakthroughs that enable full formal use in the verification.

3:00 pm - 3:30 pm

Ask the Experts Panel and closing remarks

We look forward to seeing you!

Siemens Formal Verification Team